The present invention relates to an output buffer circuit disposed in a semiconductor integrated circuit, and more particularly to a ternary output-type buffer arranged to supply an output, in the form of a ternary value, as selected from a plurality of data inputs.
A ternary output-type buffer is conventionally disposed in a peripheral circuit, for example an I/O circuit, of a memory cell array such as a SRAM or the like as shown in FIG. 8 for example. The ternary output-type buffer is arranged to supply an output in any of the states "H", "L" and "Hz" (high impedance). More specifically, the ternary output-type buffer can provide, in addition to the states "H" and "L", the state "Hz" (high impedance state) in which the output is supplied as separated from the input. Thus, a plurality of signals entered from a plurality of input terminals can successively be supplied through the common output terminal and signal line.
FIG. 9 shows the arrangement of a conventional ternary output-type buffer 600 comprising: a data input terminal 601 for receiving a data input signal Din: a control input terminal 602 for receiving a control signal En; a NOT circuit 610 for generating an inversion signal of the control signal En; a NAND circuit 620 for generating a NAND signal of the data input signal Din and the control signal En; and a NOR circuit 630 for generating a NOR signal of the data input signal Din and the signal obtained by inverting the control signal En by the NOT circuit 610; and an output circuit 640 of which output is controlled in the form of a ternary value by the NAND circuit 620 and the NOR circuit 630. The output circuit 640 comprises: a P-MOS transistor 641 having the gate for receiving, as a control signal, an output of the NAND circuit 620; an N-MOS transistor 642 which is connected, in series, to the P-MOS transistor 641 between a high-potential power source VDD and a low-potential power source GND (grounding terminal) and which has the gate for receiving, as a control signal, an output of the NOR circuit 630; and a data output terminal 603 which is led from the signal line between the transistors 641 and 642 and which is arranged to supply a data output signal Dout.
In the NAND circuit 620, there are disposed, between the high-potential power source VDD and the P-MOS transistor 641 of the output circuit 640, (i) a P-MOS transistor 621 serving as a switching element of which opening/closing is controlled by the control signal En and (ii) a P-MOS transistor 622 serving as a switching element of which opening/closing is controlled by the data input signal Din, the transistors 621 and 622 being disposed in parallel with each other. Also, there are disposed, between the gate of the P-MOS transistor 641 and the low-potential power source GND, (i) an N-MOS transistor 623 of which opening/closing is controlled by the data input signal Din and (ii) an N-MOS transistor 624 of which opening/closing is controlled by the control signal En, the transistors 623, 624 being disposed in series. In the NOR circuit 630, there are disposed, between the high-potential power source VDD and the gate of the N-MOS transistor 642, (i) a P-MOS transistor 632 of which opening/closing is controlled by the data input signal Din and (ii) a P-MOS transistor 633 of which opening/closing is controlled by the signal obtained by inverting the control signal En by the NOT circuit 610, the transistors 632, 633 being disposed in series. Also, there are disposed, between the control terminal of the output generation N-MOS transistor 642 and the low-potential power source GND, (i) an N-MOS transistor 634 of which opening/closing is controlled by the data input signal Din and (ii) an N-MOS transistor 635 of which opening/closing is controlled by the control signal En, the transistors 634, 635 being disposed in parallel.
In the ternary output-type buffer having the arrangement above-mentioned, as readily understood by executing the operations of NAND, NOT, NOR, when both the data input signal Din and the control signal En are in the state "H", the data output signal Dout is brought into the state "H". That is, there is formed an arrangement capable of supplying a ternary output by combining the NAND circuit with the NOR circuit. More specifically, the data output signal Dout is brought into the state "H" when both the data input signal Din and the control signal En are in the state "H", and the data output signal Dout is brought into the state "L" when the data input signal Din is in the state "L" and the control signal En is in the state "H", and the data output signal Dout is brought into the state "Hz" (high impedance) regardless of the state of the data input signal Din when the control signal En is in the state "L".
FIGS. 10 and 11 show conventional examples of the ternary output-type buffer capable of receiving a plurality of data signals.
FIG. 10 shows an example of prior art having a selector 500 disposed immediately before the ternary output-type buffer 600. Shown in FIG. 10 are: a first data input terminal 101A for receiving a first input signal DinA; a first control input terminal 102A for receiving a first control signal EnA which controls the output of the first input signal DinA; a second data input terminal 101B for receiving a second input signal DinB; and a second control input terminal 102B for receiving a second control signal EnB which controls the output of the second input signal DinB. The first input signal DinA and the second input signal DinB are entered through data input terminals 501, 503 in the selector 500. Either one of the input data signals is selected in the selector 500 and supplied from an output terminal 505 in the selector 500. The first control signal EnA and the second control signal EnB are entered through control input terminals 502, 503 in the selector 500. These control signals EnA, EnB control MOS transistors 508, 509 in the selector 500, and are entered into an OR circuit 507 which then generates a control signal for controlling the ternary output-type buffer 600. This control signal is supplied from a control output terminal 506. Control is made such that the first control signal EnA and the second control signal EnB are not simultaneously turned on.
In the ternary output-type buffer 600, the data signal and control signal selected or generated by the selector 500 are entered through the data input terminal 601 and the control input terminal 602. An output data signal is brought into any of three states "H", "L" and "Hz" by the NOT circuit 610, the NAND circuit 620, the NOR circuit 630 and the output circuit 640, and then supplied from an output terminal 105 through the data output terminal 603. To simplify the display of the circuit arrangement, this example uses the N-MOS transistors 508, 509 as means for selecting a data input signal Din in the selector 500. It is however required to use a ternary output-type buffer instead of N-MOS transistors in order to assure the circuit operation even with a low power voltage.
On the other hand, FIG. 11 shows an example of prior art in which a plurality of ternary output-type buffers 600A, 600B are disposed in parallel corresponding to a plurality of input data signals and control signals, and of which basic arrangement is different from that shown in FIG. 10. This ternary output-type buffer circuit is arranged such that, while controlled in state through NOT circuits 610, NAND circuits 620, NOR circuits 630 and output circuits 640 in the ternary output-type buffers 600A, 600B, the data signals are supplied to the common output terminal 105 through data output terminals 603 of the ternary output-type buffers 600A and 600B.
More specifically, to supply a signal in the form of a ternary value as selected from a plurality of data inputs, there have been employed either a method as shown in FIG. 10 in which there is added, upstream of the ternary output-type buffer, a selector for selecting one of a plurality of data inputs, or a method as shown in FIG. 11 in which ternary output-type buffers are respectively disposed for a plurality of data inputs and outputs from the buffers are supplied to the common output terminal.
However, the conventional ternary output-type buffers having the arrangements above-mentioned present the following problems.
In the arrangement in FIG. 10, as the number of inputs is increased, it is required to provide a voltage for operating the selector means such as the transistors 508, 509. This requires the use of ternary output-type buffers instead of the transistors 508, 509 in the selector 500. This increases the number of logic stages to disadvantageously lowering the signal processing speed in the selector 500. In the arrangement in FIG. 11, the drain capacitance generated in the MOS transistors at the commonly connected output stage, depends on the number of commonly connected ternary output-type buffers. This not only narrows the degree of freedom in design, but also lowers the signal processing speed due to an increase in drain capacitance.